This invention generally relates to semiconductor processing methods and more particularly to a method for forming shallow trench isolation structures.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is a preferred electrical isolation technique especially for a semiconductor chip with high integration. STI structures can be made using a variety of methods including, for example, the Buried Oxide (BOX) isolation method for shallow trenches. The BOX method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO2) which is then planarized by a plasma etched back process and/or a chemical mechanical polishing (CMP) process to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the substrate, for example, silicon, and are typically between about 0.3 and about 1.0 microns deep.
Shallow trench isolation features with trenches having submicrometer dimensions are effective in preventing latch-up and punch-through phenomena. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask, for example silicon nitride, over the targeted trench layer, for example including a PAD oxide layer, patterning a photoresist over the hard mask to define a trench feature, anisotropically etching the hard mask to form a patterned hard mask, and thereafter anisotropically etching the trench feature to form the shallow trench isolation feature. Subsequently, the photoresist is removed (e.g., stripped) and the shallow trench isolation feature is back-filled, with a dielectric material, for to example a CVD silicon oxide, also referred to as an STI oxide, followed by thermal treatment and planarization steps to remove excess materials remaining above the trench level.
One problem with prior art processes is the differing material removal rates in the CMP process used to remove excess STI oxide overlying a hard mask silicon nitride layer. In prior art processes, silicon nitride is typically used for the hard mask and acts as a polishing stop in the CMP process to remove excess overlying STI oxide. The silicon nitride is typically removed at a rate about 33 percent compared to that of the STI oxide in a typical CMP process. As a result, preferential polishing of the STI oxide filled STI trenches occurs leading to dishing over the STI trenches thereby compromising device performance.
For example, referring to FIG. 1A is shown a conceptual cross sectional view of a portion of an STI structure showing two adjacent STI trenches 12A and 12B following formation of a STI oxide layer, for example silicon oxide 18 to fill the STI trenches and to cover the hard mask silicon nitride layer 16. The hardmask layer silicon nitride layer 16 is typically formed by a low pressure chemical vapor deposition (LPCVD) process formed over a thermally grown silicon oxide layer (PAD oxide) 14 over semiconductor substrate 10, for example, silicon. Frequently, a reverse etching mask is used to remove a portion of the excess STI oxide layer 18 over active areas e.g., 18A prior to a CMP process to remove the STI oxide layer 18 overlying the silicon nitride layer 16 to define an STI feature. Referring to FIG. 1B, according to prior art processes however, during the CMP process, dishing or preferential polishing of the STI oxide takes place in the CMP process leading to recessed surfaces e.g., 12C, 12D, at the upper surface of the STI oxide filled STI feature.
Several approaches have been proposed to alleviate the CMP polishing induced defects such as dishing including inserting dummy polishing areas around the STI features designed to reduce the effect of dishing and adding an additional metal nitride overlayer to act as an additional polishing stop. These approaches, while having limited success, have the effect of increasing processing steps and therefore increase operating costs while reducing a throughput.
Therefore, there is a need in the semiconductor processing art to develop an improved method for forming shallow trench isolation features whereby CMP processing induced defects are avoided or reduced while improving a production throughput.
It is therefore an object of the invention to provide an improved method for forming shallow trench isolation features whereby CMP processing induced defects are avoided or reduced while improving a production throughput while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing preferential chemical mechanical polishing (CMP) of a silicon oxide filled shallow trench isolation (STI) feature during an STI formation process.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface including active areas for forming semiconductor devices thereon; forming a silicon oxynitride layer over the process surface for photolithographically patterning STI trenches around the active areas; photolithographically patterning STI trenches around the active areas for anisotropic etching; anisotropically etching the STI trenches extending through the silicon oxynitride layer into the semiconductor wafer; depositing a silicon oxide layer over the silicon oxynitride layer to include filling the STI trenches; and, performing a CMP process to remove the silicon oxide layer overlying the silicon oxynitride layer to reveal an upper surface of the silicon oxynitride layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.